The present invention relates to a nonvolatile memory apparatus permitting rescue from faults by redundancy, and more particularly to a technique that can be effectively applied to a nonvolatile memory apparatus permitting electrical rewriting, such as a flash memory.
In volatile memories including static random access memories (SRAMs and dynamic random access memories (DRAMs) as well as in nonvolatile memories including flash memories, memory cells and bit lines are rescued from faults by providing redundancy in a memory array. This rescue from faults is accomplished by having faulty addresses corresponding to faulty memory cells and bit lines stored, determining with an access address supplied from outside whether or not the memory cells and bit lines to be accessed include any faulty memory cell or bit line indicated by a faulty address (hereinafter referred to as faulty address determination) and, if they include any redundant memory cell, which corresponds to a rescuing address, is made accessible in place of the faulty memory cell or bit line. Patent Reference 1 discloses a nonvolatile memory having redundancy for rescue from faults, more particularly a configuration in which faulty addresses are stored in the memory cells of a nonvolatile memory and a rescuing address is read into a latch and made available for use when the power supply is turned on.
Patent Reference 1: Japanese Unexamined Patent Publication No. 2004-55100